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Compact and high-speed hardware architectures for hash function tiger

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2 Author(s)
Satoh, A. ; Nat. Inst. of Adv. Ind. Sci. & Technol., Tokyo, Japan ; Sklavos, N.

Compact and high-speed hardware architectures for the 192-bit hash function Tiger are proposed and their gate counts and throughputs are evaluated using a 90-nm CMOS standard cell library. The implementations achieve practical performances of 22.5 K with 2.2 Gbps and 46.4 Kgates with 6.95 Gbps. These throughputs are 1.5-2 times higher than those of the SHA hash family SHA-256/-512, but the hardware efficiencies (defined as throughput per gate) of Tiger are lower than those of SHA and are half those of the Whirlpool hash function. Hardware performance is one of the most important features for hash functions to be selected as a next standard algorithm after SHA. Therefore, the requirements for hash functions to achieve flexible and high-performance circuits are also clarified through this study by analyzing the characteristics of structure and basic components of each algorithm from the viewpoint of hardware implementation.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009