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23-mW 50-MS/s 10-bit pipeline A/D converter with nonlinear LMS foreground calibration

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3 Author(s)
Takashi Oshima ; Hitachi Ltd., Central Research Laboratory, 1-280 Higashi-koigakubo, Kokubunji-shi, Tokyo 185-8601, Japan ; Tomomi Takahashi ; Taizo Yamawaki

A novel nonlinear foreground calibration of pipeline A/D converters based on LMS algorithm has been proposed and verified by macro-based simulation as well as measurement of test chip. The prototype 23-mW 50-MS/s 10-bit pipeline ADC in 0.13-mum CMOS has confirmed that the proposed calibration can accurately and rapidly correct the inaccuracy caused both by heavy nonlinearity of low-gain op-amps and by their incomplete settling without requiring any dedicated voltage references, complicated structures or timing sequence and hence can be used for various applications.

Published in:

2009 IEEE International Symposium on Circuits and Systems

Date of Conference:

24-27 May 2009