By Topic

A reverse-encoding-based on-chip AHB bus tracer supporting both Post-T and Pre-T trace

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fu-Ching Yang ; Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Cheng-Lung Chiang ; Ing-Jer Huang

This demonstration shows how we can enable the SoC debugging and performance evaluation with the reverse-encoding-based on-chip AHB bus tracer. By embedding this bus tracer to a SoC, designers can observe and debug the SoC internal states easily. The bus tracer supports both Pre-Triggering (Pre-T) trace and Post- Triggering (Post-T) trace at high compression ratio. For Post-T trace, designs can monitor signals for a known period at different abstraction level. It is very helpful for designs to realize the top view and detail view of the system for performance evaluation and debugging. Pre-T trace captures signals before an event occurs. It is very helpful for system error diagnosis since the errors are unexpected.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009