By Topic

Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Junha Im ; School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea ; Misuk Cho ; Yunho Jung ; Jaeseok Kim

In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-mum CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130 Mbps. The logic gate count for the processor is 978 K and the power consumption is 62/284 mW (TX / RX), respectively.

Published in:

2009 IEEE International Symposium on Circuits and Systems

Date of Conference:

24-27 May 2009