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In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-mum CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130 Mbps. The logic gate count for the processor is 978 K and the power consumption is 62/284 mW (TX / RX), respectively.