This paper presents an architecture design and implementation of an iterative receiver for linearly precoded MIMO systems. The receiver is composed of two main elements: an MMSE-IC equalizer and a 64-state MAX-LOG-MAP decoder which exchange soft information through an interleaving scheme. Each block of the architecture was designed to reach a trade off between complexity and error rate performance. Our objective is to validate the potential of iterative receiver as practical and competitive solution for linearly precoded MIMO systems.
Published in:
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Date of Conference: 24-27 May 2009