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Reduction of loop delay for digital symbol timing recovery systems using asynchronous equalization

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3 Author(s)
Chien, Ying-Ren ; Integrated Syst. Lab., Nat. Taiwan Univ., Taipei, Taiwan ; Chu-Yun Lin ; Hen-Wai Tsao

Timing recovery loops with low loop delay are desirable. This paper presents receiver architectures with asynchronous equalization to reduce the loop delay. We propose a new asynchronous delayed least-mean-square (AD-LMS) adaptation algorithm together with an interaction-free loop to eliminate interaction between timing and equalization loops. In addition, a timing recovery scheme to reduce the timing jitter is developed. The proposed architecture can apply to 10 GBASE-T systems. Simulation results show that the conventional approach suffers from the loop-interaction and the proposed method can eliminate this issue. Moreover, our approach has high phase margin, low gain peaking, and low jitter properties.

Published in:

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date of Conference:

24-27 May 2009