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Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric

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2 Author(s)
Zheng Wang ; Dept. of Comput. Sci. & Eng., Texas A&M Univ., College Station, TX, USA ; Walker, D.M.H.

This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs.

Published in:

VLSI Test Symposium, 2009. VTS '09. 27th IEEE

Date of Conference:

3-7 May 2009

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