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An Adaptive-Rate Error Correction Scheme for NAND Flash Memory

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4 Author(s)
Te-Hsuan Chen ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Yu-Ying Hsiao ; Yu-Tsao Hsing ; Cheng-Wen Wu

ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level.

Published in:

VLSI Test Symposium, 2009. VTS '09. 27th IEEE

Date of Conference:

3-7 May 2009