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Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

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1 Author(s)
Sapatnekar, S.S. ; Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

An efficient solution to the wire sizing problem using the Elmore delay model is proposed. Two formulations of the problem are put forth. In the first, the minimum interconnect delay is sought, while in the latter, we minimize the net delay under delay constraints at the leaf nodes; previous approaches solve only the former problem. Theoretical results on these problems are proved, and two algorithms are presented. One is a sensitivity-based heuristic, while the other is a rigorous convex optimization problem. It is shown experimentally that the sensitivity-based heuristic gives near-optimal results with reasonable runtimes. A smooth area-delay tradeoff is shown, and results are presented to illustrate the fact that sizing for minimum delay is not a good engineering goal. Instead, a delay goal of even 15% over the minimum provides significantly better engineering solutions

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 8 )