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A 1.3-ns 32-word×32-bit three-port BiCMOS register file

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2 Author(s)
Chin-Chieh Chao ; Center for Integrated Syst., Stanford Univ., CA, USA ; B. A. Wooley

This paper describes a CMOS multiport static memory cell with which it is possible to use current-switching bipolar peripheral circuits to maintain small voltage swings throughout the read access path while retaining the high density of CMOS memory arrays. An experimental 32-word×32 bit three-port register file has been designed and implemented using this cell. The register file was fabricated in a 0.6-μm BiCMOS technology and operates from a single -3.3-V power supply with ECL-compatible I/O circuits. Under nominal operating conditions at 20°C, the measured pin-to-pin access time is 1.3 ns. The minimum write enable pulse width required is less than 1 ns, and the power dissipation, excluding the output buffers, is 650 mW at a clock rate of 100 MHz

Published in:

IEEE Journal of Solid-State Circuits  (Volume:31 ,  Issue: 6 )