By Topic

A 36 V Programmable Instrumentation Amplifier With Sub-20 \mu V Offset and a CMRR in Excess of 120 dB at All Gain Settings

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

A 36 V capable programmable gain instrumentation amplifier (PGA) is presented with sub-20 muV offset, sub-0.2 muV/degC offset drift and a common-mode rejection (CMRR) that exceeds 120 dB at all gain settings without any trimming. It is the first 36 V capable precision PGA implemented in a high-voltage CMOS process, which, in addition, incorporates several additional functions, such as the detection of input and output fault conditions, provisions for improving system-level settling time and an input switch network. All op-amps used in the PGA employ chopper stabilization with a notch filter that removes chopping glitches, leading to low offset and drift and no 1/f noise. The PGA has a total of 22 gain steps (binary steps between 1/8 to 128, each with an optional multiplying factor of 1 or 1.375) with better than 0.1% gain accuracy, < 0.001% nonlinearity and sub-2 ppm/C gain drift. The input switch network, in addition to acting as a 2-channel multiplexer, also enables various system-level diagnostic features. The PGA is implemented in a 0.35 mum CMOS process with a 36 V extension, has a 3.6 times 2.4 mm chip area and consumes a total quiescent current of 3 mA.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 7 )