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A 5-Gbps Test System for Wafer-Level Packaged Devices

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2 Author(s)
Ashraf M. Majid ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; David C. Keezer

This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2-5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a plusmn 18-ps timing accuracy. The generated signals exhibit low jitter ( ~ 35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.

Published in:

IEEE Transactions on Electronics Packaging Manufacturing  (Volume:32 ,  Issue: 3 )