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On minimizing the number of test points needed to achieve complete robust path delay fault testability

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3 Author(s)
Uppaluri, P. ; Avant Corp., Research Triangle Park, NC, USA ; Sparmann, U. ; Pomeranz, I.

Recently, Pomeranz and Reddy (1994), presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at reducing this number. Indirectly, this approach achieved complete robust path delay fault testability in very low computation times. In this paper, we use their test application scheme, however, we use more exact measures for guiding test point insertion like test generation and RD fault identification. Thus, we reduce the number of test points needed to achieve complete testability by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable. Experimental results show that an average reduction of about 70% in the number of test points over the approach of Pomeranz and Reddy can be obtained

Published in:

VLSI Test Symposium, 1996., Proceedings of 14th

Date of Conference:

28 Apr-1 May 1996

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