Cart (Loading....) | Create Account
Close category search window

Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Vazquez, D. ; Centro Nacional de Microelectron., Seville Univ., Spain ; Huertas, J.L. ; Rueda, A.

This paper focuses on the implementation of the `sw-op amp' concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell

Published in:

VLSI Test Symposium, 1996., Proceedings of 14th

Date of Conference:

28 Apr-1 May 1996

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.