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A self-driven test structure for pseudorandom testing of non-scan sequential circuits

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2 Author(s)
Muradali, F. ; Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada ; Rajski, J.

Introduced is a self-driven test point structure which permits at-speed, on-chip, non-scan, sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. The test network is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. High single stuck-at fault coverage is achieved for a number of ISCAS-89 benchmarks

Published in:

VLSI Test Symposium, 1996., Proceedings of 14th

Date of Conference:

28 Apr-1 May 1996