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Serendipitous SEU hardening of resistive load SRAMs

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6 Author(s)
Koga, R. ; Aerosp. Corp., Los Angeles, CA, USA ; Kirshman, J.F. ; Pinkerton, S.D. ; Hansel, S.J.
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High and low resistive load versions of Micron Technology's MT5C1008C (128K×8) and MT5C2561C (256K×1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load. A substantially larger number of multiple-bit errors was observed for the low resistive load SRAMs, which also exhibited a “1”→“0” to “0”→“1” bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations

Published in:

Nuclear Science, IEEE Transactions on  (Volume:43 ,  Issue: 3 )

Date of Publication:

Jun 1996

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