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Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

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4 Author(s)
Gabara, T. ; AT&T Bell Labs., Murray Hill, NJ ; Fischer, W. ; Harrington, J. ; Troutman, W.

Measurements of a 0.5 μm CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5× and 2×, respectively. A single external resistor is required to set a reference current

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996