By Topic

Implementing and evaluating adiabatic arithmetic units

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Knapp, M.C. ; Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA ; Kindlmann, Peter J. ; Papaefthymiou, M.C.

In recent years, several adiabatic logic architectures have been proposed for low-power VLSI design. However, no work has been presented describing the implementation and evaluation of nontrivial adiabatic circuits. We have evaluated a specific adiabatic architecture and used it in the design of low-power arithmetic units. We investigated implementation issues specific to adiabatic system development and performed a systematic comparison of our designs with corresponding CMOS circuits. In this paper we describe our adiabatic designs, discuss implementation issues at the logic and architectural level, and report our empirical findings

Published in:

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Date of Conference:

5-8 May 1996