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Design of a tokenless architecture for parallel computations using associative dataflow processor

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2 Author(s)
T. Jamil ; Comput. Eng. Program, Florida Inst. of Technol., Melbourne, FL, USA ; R. G. Deshmukh

The currently existing models of computation, control-flow and data-flow, have their limitations and weaknesses in utilizing parallelism adequately. A new refined model of computation, called associative dataflow, has been previously proposed in the literature which attempts to circumvent the bottlenecks inherent in conventional dataflow using associative memories. In this new model of computation, a dataflow graph is conceptually assumed to be upside-down and the computation is divided into two phases, namely the search phase and the execution phase. During the search phase, each node at the top of the hierarchy, called the parent, attempts to find the nodes connected to it in the dataflow graph, called the children. During the execution phase, the operations are carried out as in conventional dataflow paradigm. The limitations and weaknesses associated with control-flow and data-flow are described, leading to the proposed concept of associative dataflow. Simulation results of existing dataflow systems are compared with the associative dataflow model to support the fact that the new model of computation provides faster execution time and better ALU utilization than the conventional models. The design of an associative dataflow system is described by providing as much detail as can possibly be incorporated to understand the concept with reference to existing computer systems. Finally, specifications of the designed system are outlined by listing important characteristics of the associative dataflow system

Published in:

Southeastcon '96. Bringing Together Education, Science and Technology., Proceedings of the IEEE

Date of Conference:

11-14 Apr 1996