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Graph modeling of parallelism in superscalar architecture-a case study of HP PA-RISC microprocessor

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4 Author(s)
Malek, M. ; Ins. fur Inf., Humboldt-Univ., Berlin, Germany ; Chillakanti, P. ; Shaikh, S.A. ; Sinha, A.

Extracting instruction level parallelism is a key issue in superscalar architecture. We propose a graph theoretic model to identify parallelism in a sequence of instructions. The system graph model (SGM), presented, is a fundamental source of information regarding the resource dependencies, intra-instruction and inter-instruction parallelism, and the cost-performance of the architecture. Additionally, we propose a new technique called hierarchical identification of parallelism (HIP), which is a systematic approach to identify parallelism. Using this technique, an optimizing compiler can obtain a better static schedule of the assembly level instructions. For better understanding of the techniques developed, we have presented a case study of Hewlett-Packard's PA-RISC microprocessor. Finally, we discuss potential application of the proposed graph model in architectural level testing

Published in:

Southeastcon '96. Bringing Together Education, Science and Technology., Proceedings of the IEEE

Date of Conference:

11-14 Apr 1996

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