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Performance model for a prioritized multiple-bus multiprocessor system

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2 Author(s)
John, L.K. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Yu-Cheng Liu

The performance of a shared memory multiprocessor system with a multiple-bus interconnection network is studied in this paper. The effect of bus and memory contention is modeled using a probabilistic model and a closed form solution for the acceptance probability of each processor is presented. It is assumed that each processor in the system has a distinct priority assigned to it and that arbitration is based on priority. Whenever a request from a processor is rejected due to bus or memory conflicts, the request is resubmitted until granted. Based on the model, individual processor acceptance probabilities are first estimated, from which the effective memory bandwidth is computed. The accuracy of the analytical model is verified based on simulation results. Results from the model are compared against other approximate models previously reported in literature. It is observed that the inaccuracy of the model measured in terms of error from simulation results is less than that in previously reported studies

Published in:

Computers, IEEE Transactions on  (Volume:45 ,  Issue: 5 )

Date of Publication:

May 1996

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