Cart (Loading....) | Create Account
Close category search window
 

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Byungsoo Chang ; Dept. of Electron. Eng., Seoul Nat. Univ., South Korea ; Joonbae Park ; Kim, Wonchan

A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 μm CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for the high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 5 )

Date of Publication:

May 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.