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Adding instruction cache effect to schedulability analysis of preemptive real-time systems

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5 Author(s)
Busquets-Mataix, J.V. ; Dept. de Ingenieria de Sistemas, Computadores y Autom., Univ. Politecnica de Valencia, Spain ; Serrano, J.J. ; Ors, R. ; Gil, P.
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Cache memories are commonly avoided in real time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. The paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to both cache partitioning (increase of the cache predictability by assigning private cache partitions to tasks) and CRMA (Cached RMA: cache effect is incorporated in the utilization based rate monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA, however the partitioning scheme may be better depending on the system configuration. The obtained results bound the applicability domain for each method for a variety of hardware and workload configurations. The results can be used as design guidelines

Published in:

Real-Time Technology and Applications Symposium, 1996. Proceedings., 1996 IEEE

Date of Conference:

10-12 Jun 1996