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Entry mobile phone market is a mass volume segment where the modem and application technologies are commoditized and fully proven. Nevertheless the cost and power reduction target continues to heavily drive leading edge innovations. Semiconductor companies strive to integrate more and more Printed Circuit Board (PCB) components into one single chip, without discontinuing the technology node shrink roadmap, from 130 nm down to 65 nm. This duality between integration level and aggressive silicon feature size reduction generates an innovative environment where design engineers must create new methodologies to cope with complex cross coupling mechanisms and additional power dissipation. This paper describes one aspect of the design methodology to reduce the die and package cross-talks, and focus on the package co-design flow. The chip being considered is a 65 nm single chip System on Chip (SoC) including EDGE RF, Power Management Unit (PMU), Audio Front End (AFE) and FM Radio (FMR) circuits.