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System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

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8 Author(s)
Facchini, M. ; IMEC - Interuniversity Microelectron. Center, Heverlee ; Carlson, T. ; Vignon, A. ; Palkovic, M.
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Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottle-neck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-the-art industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.

Published in:

Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.

Date of Conference:

20-24 April 2009