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On-chip communication architecture exploration for processor-pool-based MPSoC

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3 Author(s)
Young-Pyo Joo ; School of EECS, Seoul National University, Korea ; Sungchan Kim ; Soonhoi Ha

MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP-based MPSoC is extremely wide, application-specific optimization of on-chip communication is a nontrivial task. This paper presents a systematic methodology for on-chip network design of PP-based MPSoC. The proposed approach allows independent configurations of PPs, which leads to efficient solutions than previous work. Since time-consuming simulation is inevitable to evaluate complicated on-chip network during exploration, we do early pruning of design space by a bandwidth analysis technique that considers task execution dependencies. Our approach yields the Pareto-optimal solutions between clock frequency and area requirements. The experiments show that the proposed technique finds more efficient architectures compared with the previous approaches.

Published in:

2009 Design, Automation & Test in Europe Conference & Exhibition

Date of Conference:

20-24 April 2009