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SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems

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2 Author(s)
Abelardo Jara-Berrocal ; NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, University of Florida, Gainesville, 32611, USA ; Ann Gordon-Ross

Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applications are decomposed into multiple computational modules (tasks) that collectively operate and communicate in parallel. In this paper, we present a scalable and highly parametric streams-based communication architecture for inter-module communication for FPGA-based systems - SCORES. This communication architecture improves on previous methods by providing increased application specialization and heterogeneous module clock frequencies, as well as providing a means for low latency communication and data throughput guarantees.

Published in:

2009 Design, Automation & Test in Europe Conference & Exhibition

Date of Conference:

20-24 April 2009