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An ILP formulation for task mapping and scheduling on multi-core architectures

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5 Author(s)
Ying Yi ; University of Edinburgh, The King's Buildings, Mayfield Road, Edinburgh, EH9 3JL, UK ; Wei Han ; Xin Zhao ; Ahmet T. Erdogan
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Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target multi-core architecture, achieving up to 1.3times parallel efficiency by employing only two dynamically reconfigurable processor cores.

Published in:

2009 Design, Automation & Test in Europe Conference & Exhibition

Date of Conference:

20-24 April 2009