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Performance analysis for an important class of parallel-processing networks

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1 Author(s)
Ziavras, S.G. ; Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

This paper presents performance and feasibility analyses for important mesh-connected architectures that contain sparse broadcast buses. Two basic architectures, that implement bus intersections differently, are given special attention. The first architecture simply allows row/column bus crossovers. The second architecture has separable buses and implements such intersections with switches for further flexibility. Both architectures have lower cost than the mesh with multiple broadcast, which has buses spanning each row and each column, but the former architectures maintain to a high extent the powerful properties of the latter mesh. The architecture with separable buses is shown to often perform better than the higher-cost mesh with multiple broadcast. Architectures with separable buses that employ store-and-forward routing often perform better than architectures with contiguous buses that employ high-cost wormhole routing. All these architectures are evaluated in reference to cost, and efficiency in implementing several important operations and application algorithms. The results prove that these architectures are very promising alternatives to the mesh with multiple broadcast; in addition, their implementation is cost-effective and feasible

Published in:

Parallel Architectures, Algorithms, and Networks, 1996. Proceedings., Second International Symposium on

Date of Conference:

12-14 Jun 1996

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