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Design and FPGA implementation of iterative decoders for codes on graphs

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3 Author(s)
Sivasubramanian, B. ; Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC ; Gross, W.J. ; Leib, H.

This work presents a field programmable gate array (FPGA) implementation of the min-sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the min-step in the min-sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the min-sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.

Published in:

Electrical and Computer Engineering, 2009. CCECE '09. Canadian Conference on

Date of Conference:

3-6 May 2009