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Design and implementation of a high speed parallel architecture for ATM UNI

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4 Author(s)
Wen-Yu Tseng ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chin-Chou Chen ; Wei, D.S.L. ; Sy-Yen Kuo

In this paper, a parallel architecture is proposed to support the operations described in the ITU-T Recommendation I.432 (B-ISDN user-network interface-Physical layer specification). It is rather difficult to perform their operations on a bit serial architecture at a high rate. This paper demonstrates how these tasks can be achieved by means of parallelism. First, we describe the user-network interfaces in general and their physical layer properties. Then a parallel architecture is proposed with a general translation method which converts the serial operation into the parallel one. The application of the parallel architecture on each function is also depicted and the system has been realized in hardware using CMOS technology

Published in:

Parallel Architectures, Algorithms, and Networks, 1996. Proceedings., Second International Symposium on

Date of Conference:

12-14 Jun 1996