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Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

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2 Author(s)
Jung-Sheng Chen ; Power Conversion Taiwan, Fairchild Semicond. Corp., Hsinchu, Taiwan ; Ming-Dou Ker

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 8 )