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This paper investigates the program saturation in aggressively scaled interpoly dielectric (IPD) floating-gate (FG) cells for nand application. To describe the program saturation in IPD stacks containing thick suboxides (ges 4 nm) , a simple model was developed, directly yielding the maximum reachable programmed threshold voltage level for a given FG cell geometry. The presented model agrees very well to program saturation measurements carried out on a 48 nm FG nand technology with an IPD composed of SiO2 and Al2O3. By extending the considerations to an arbitrary IPD, this paper represents the first attempt to quantify the IPD current blocking ability required for future scaled FG memory cells.