By Topic

An Investigation on Anomalous Hot-Carrier-Induced On-Resistance Reduction in n-Type LDMOS Transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Chen, Jone F. ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Kuen-Shiuan Tian ; Shiang-Yu Chen ; Kuo-Ming Wu
more authors

In this paper, on-resistance (R on) degradation induced by hot-carrier injection in n-type lateral diffused metal-oxide-semiconductor transistors with shallow trench isolation (STI) in the drift region is investigated. R on unexpectedly decreases under medium- and high-gate voltage (V gs) stress conditions. According to experimental data and technology computer-aided-design simulation results, the mechanisms responsible for anomalous R on shift are proposed. When the device is stressed under medium V gs, hot-hole injection and trapping occur at the STI edge closest to the channel, resulting in R on reduction. Interface trap generation (??N it) occurs at the STI edge closest to the channel and nearby drift region, leading to R on increase. For the device stressed under high V gs, R on reduction is also attributed to hole trapping at the STI corner closest to the channel. ??N it created by hot-electron injection at the STI edge closest to the drain dominates device characteristics and leads to R on increase eventually. Based on the proposed R on degradation mechanisms, an R on degradation model is discussed and verified with experimental data.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:9 ,  Issue: 3 )