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A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

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7 Author(s)
H. Murakami ; Microelectron. Eng. Lab., Toshiba Corp., Kawasaki, Japan ; N. Yano ; Y. Ootaguro ; Y. Sugeno
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This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication followed by 64 b addition) per cycle at 56.5 MHz. The area is 2.35 mm2 with 0.4 μm CMOS technology

Published in:

IEEE Journal of Solid-State Circuits  (Volume:31 ,  Issue: 7 )