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Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

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3 Author(s)
Kanan, R. ; Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland ; Hochet, B. ; Declercq, M.

This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FET's only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 μm MESFET process. The power consumption of an inverter is about 10 μW at 100 MHz

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Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 7 )