Referenced Items are not available for this document.
A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:31
,
Issue:
7
)
Date of Publication: Jul 1996
- Page(s):
- 890 - 897
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5319504
- Digital Object Identifier :
- 10.1109/4.508200
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jul 1996
- Sponsored by :
- IEEE Solid-State Circuits Society
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