Cart (Loading....) | Create Account
Close category search window

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Craninckx, J. ; ESAT, Katholieke Univ., Leuven, Heverlee, Belgium ; Steyaert, M.S.J.

A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:31 ,  Issue: 7 )

Date of Publication:

Jul 1996

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.