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A manufacturable high performance quarter micron CMOS technology using I-line lithography and gate linewidth reduction etch process

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8 Author(s)
Thakar, G.V. ; Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA ; McNeil, V.M. ; Madan, S.K. ; Riemenschneider, B.R.
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This paper reports the successful application of I-line lithography to fabricate high performance quarter micron CMOS integrated circuits with good linewidth control and excellent edge profile for poly gate. This is accomplished using an overetch with the bottom antireflection coating dry-etch to decrease the linewidth of resist before poly etch. This etch bias shifts the linear portion of the exposure curve to smaller final linewidths. This technology can be extended to 0.12 /spl mu/m CMOS by adding hammerheads to the end of poly gates to prevent end-of-line pull back and rounding. The maximum useful Figure of Merit (FOM) is the FOM at that gate length for which inverter chain active and standby currents are equal. 1/FOM(max) is 32 ps for V/sub DD/=2.5 V and 1 MHz clocks. For 300 MHz clock and V/sub DD/=2.5 V 1/FOM(max) is 23 ps. Lowering V/sub DD/ to 1.2 V results in 1/FOM(max) of 40 ps for 300 MHz clock. SRAM arrays with high yield and functionality down to 1 V have been obtained.

Published in:

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Date of Conference:

11-13 June 1996