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Hybrid phase locked loop system for PRML disk drive read channels

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2 Author(s)
Kovacs, J. ; Analog Devices Inc., Wilmington, MA, USA ; McCall, K.

This paper describes a mixed signal Phase Locked Loop sub-system in a Partial Response Maximum Likelihood (PRML) disk drive read channel IC fabricated on a single poly, dual metal 0.6 u, 5 V foundry CMOS process. The PLL provides programmable damping factor and gain control over a 25-200 MHz frequency range. A non-linear ADC improves its robustness when processing asymmetrical input signals. Acquisition time is reduced by instantaneously adjusting the start-up phase of its clock output.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996