By Topic

A data recovery circuit for burst signal using 440 MHz CMOS direct phase controlled VCO

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Yoshida, A. ; Integrated Designing Div., Oki Electr. Ind. Co. Ltd., Tokyo, Japan ; Taya, T. ; Yamaoka, N. ; Matsumoto, S.
more authors

A clock and data recovery circuit is a key element in communication systems for realizing high speed signal transfers. In passive optical transmission systems, a data recovery circuit for burst data is indispensable. A burst-mode clock and data recovery circuit using gated VCOs has been reported. We have proposed data recovery circuits for a continuous bit stream using the direct phase controlled VCO (DPC-VC0) where the oscillation phase of the VCO is directly controlled by the trigger signal extracted from the input data. This paper proposes a data recovery circuit for burst data using the DPC-VCO in a 0.5um CMOS process.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996