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A 960 Mbps/pin interface for skew-tolerant bus using low jitter PLL

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6 Author(s)
Sungjoon Kim ; Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., South Korea ; Kyeongho Lee ; Yongsam Moon ; Deog-Kyoon Jeong
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This paper describes an I/O scheme for use as a high-speed bus which eliminates setup and hold time requirements between clock and data by using oversampling method. The I/O circuit uses low jitter PLL which suppresses the effect of supply noise. Two experimental chips with 4 pin interface have been fabricated with 0.6 /spl mu/m CMOS technology, which exhibits the bandwidth of 960 Mbps per pin.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996