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Demonstration of 5T SRAM and 6T dual-port RAM cell arrays

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1 Author(s)
H. Tran ; Texas Instrum. Inc., Dallas, TX, USA

This paper describes new circuit techniques that provide robust operations for a five transistor, single bitline SRAM cell design. The techniques have been implemented in an array of six transistor memory cells and operated as a dual-port RAM. The array has been fabricated using 0.6 /spl mu/m CMOS technology, and the test results show the array is capable of operating as a dual-port memory over a wide voltage supply range.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996