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A power-optimized CMOS baseband channel filter and ADC for cordless applications

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4 Author(s)
Cho, T.B. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Chien, G. ; Brianti, F. ; Gray, P.R.

A 3.3 V continuous-time anti-aliasing filter, 8th-order switched-capacitor channel filter and 10-bit ADC implemented in 0.6 micron CMOS for baseband channel filtering in direct conversion cordless phone receivers realizes an overall gain of 50 dB with 42 dB of gain control range. Dynamic range of the combined filter section is 87 dB, and the maximum SNDR of ADC is 54 dB at 40 MS/s. Total power dissipation of 48 mW for filters and ADC is achieved at 3.3 volts through optimum capacitor scaling in filter and pipeline ADC implementation.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996