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A fully integrated low noise RF frequency synthesizer design for mobile communication application

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3 Author(s)
Seog-Jun Lee ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Beomsup Kim ; Kwyro Lee

A fully monolithic PLL frequency synthesizer circuit implemented in a 0.8 /spl mu/m CMOS technology is presented. The measured result shows a frequency range of 700 MHz to 1 GHz with -100 dBc/Hz phase noise at a 1 MHz carrier offset. The test chip consumes 125 mW at maximum frequency from a 5 V supply. No external components are used except a passive filter and supply decoupling capacitors.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996

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