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Discusses a self-configurable digital neuro chip which addresses a multi-network architecture designed for a large number of characters or image recognition system. Recently neuro chips which operate at high speed have been developed by using technologies of multiprocessor. However those neurochips are very expensive because of needs of large memory for synaptic weights and are not suitable for recognition with a large number of categories. In order to obtain better recognition performance with less memory we had to determine optimum network size and some parameters by trial and error. Thus we have proposed an original proliferating neuron model and a multi neural network (NN) model, originated two new schemes, DSP architecture suitable for a proliferating neuron and method of addressing to multi-network and fabricated in 0.5 /spl mu/m CMOS process. As a result. amount of total memory was dramatically reduced to 9%. This chip can classify up to 16,384 categories with performance of 1.75 msec/character on a single chip and can make the recognition system more compact and of lower cost.
Date of Conference: 13-15 June 1996