By Topic

Power-on contention elimination [CMOS digital circuits]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Taylor, G. ; Intel Corp., Hillsboro, OR, USA ; Wong, K.

If ignored, power-on contention will eventually become intolerable. If ignored on current processes it will lead to increased fallout at burn-in. On future processes it may lead to fallout at the normal operating supply for a chip. Fortunately, a straightforward design solution is available which permits a chip to avoid power-on contention failures. The authors describe this design solution.

Published in:

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Date of Conference:

13-15 June 1996