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A duty cycle correction circuit (DCC) for high frequency clocks with fine resolution is designed and tested at 1.2 V in 90 nm CMOS process. Spice simulations show that this duty cycle corrector can adjust the output duty cycle to 50 plusmn 0.5% with input clock at 500 MHz and input duty cycle ranging from20% to 80%. DCC will not introduce any delay in the forward path, which makes it suitable for multi-phase clock applications. The proposed implementation uses the high frequency delay line and MUTEX (mutual exclusion element) based circuit for achieving high resolution.
Date of Conference: 13-15 May 2009