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A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits

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2 Author(s)
Koustav Bhattacharya ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL ; Nagarajan Ranganathan

The rates of transient faults such as soft errors have been significantly impacted due to the aggressive scaling trends in the nanometer regime. In the past, several circuit optimization techniques have been proposed for preventing soft errors in logic circuits. These approaches include, inclusion of concurrent error detection circuits on selective nodes, selective gate sizing, dual-VDD assignment and selective node hardening at the transistor level. However, we show in this paper that larger wirelengths for nets can act as larger RC ladders and can effectively filter out the transient glitches due to radiation strikes. Based on this, we propose a simulated annealing based placement algorithm that significantly reduces the SER of logic circuits. We accurately capture the soft error masking effects by using a new metric called the logical observability. The cost function for simulated annealing is modeled as the summation of the logical observability weighted with the netlength for each net, while simultaneously constraining the total area and the total wirelength. The algorithm tries to assign higher wirelengths for nets with low masking probability for higher glitch reduction, while maintaining low delay and area penalty for the overall circuit. Each placement configuration is represented as a sequence pair and the moves in the space of sequence pairs are probabilistically accepted depending upon the cost gradient and the iteration count. Higher cost moves have a higher probability of acceptance at initial iterations for better state space exploration, while at later iterations the algorithm greedily tries to minimize the cost. To the best of our knowledge, this is the first time that soft error rate reduction is attempted during the placement stage. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks. We have experimented using the FreePDK 45nm Process Design Kit and the OSU cell library which indicate that our radiation immune plac- ement algorithm can significantly reduce the SER in logic circuits with very low overheads in delay and area.

Published in:

2009 IEEE Computer Society Annual Symposium on VLSI

Date of Conference:

13-15 May 2009