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Noise Minimization of MOSFET Input Charge Amplifiers Based on \Delta \mu and \Delta {\rm N} 1/f Models

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2 Author(s)
Giuseppe Bertuccio ; Dept. of Electron. Eng. & Inf. Sci., Politec. di Milano, Como ; Stefano Caccia

The optimization of the noise performance of integrated complementary metal-oxide semiconductor (CMOS) charge amplifiers is studied in detail considering accurate 1/f noise modeling for the input metal-oxide semiconductor field-effect transistor (MOSFET) biased in a strong inversion-saturation region. This paper aims to generalize and correct previously published analyses which have been based on two limiting and sometimes not applicable assumptions: a fixed MOSFETs bias current and the general validity of the McWhorter 1/f noise model. This study considers the two main 1/f noise models: (1) the mobility fluctuation, known as Deltamu or Hooge model, which is followed by p-channel MOSFETs and (2) the carriers number fluctuation, also known as DeltaN or McWhorter model, which is applicable only for n-channel MOSFETs. The front-end noise optimization is made with the 1/f component alone, thus determining the ultimate performance, and also considering the presence of series and parallel white noise sources. It is shown that different design criteria are valid of p- or n-channel MOSFETs: the Deltamu model results in an optimum bias current and a different optimum gate width with respect to DeltaN model. Two-dimensions suboptimum noise minimization criteria are derived when power or area constraints are imposed to the circuit design. Starting from experimental data on CMOS 1/f noise, examples of application of the presented analysis are shown to predict the lower limits of the 1/f noise contribution for the currently available CMOS technologies.

Published in:

IEEE Transactions on Nuclear Science  (Volume:56 ,  Issue: 3 )